1. Field of the Invention
The present invention relates to a multiprocessor system including plural processors, and more particularly to a boot-up method of a slave system used in a multiprocessor system including a master system and a slave system.
2. Description of Related Art
As a solution to the problem of how to improve a performance of a built-in device and save power, attentions have been paid to a multiprocessor system including plural processor cores (see “Multicore” in Embedded Field, Tasks of Enabling Multi-function in hardware/software component, Outline and packaging example of OS”, YOSHIDA Masayasu, HONDA Shinya, Design Wave Magazine, August issue, 2005, CQ publishing Co., Ltd., for example).
FIG. 4 is a diagram of a conventional multiprocessor system. As shown in FIG. 4, the conventional multiprocessor system includes a master system 10 and a slave system 20. The master system 10 includes a CPU (Central Processor Unit) 11, a RAM (Random Access Memory) 12, a program ROM (Read Only Memory) 13, and a data interface (I/F) circuit 14. Similar to the master system 10, the slave system 20 includes a CPU 21, a RAM 22, a program ROM 24, and a data interface (I/F) circuit 23.
In the Related Art of FIG. 4, the master system 10 and the slave system 20 each includes a program ROM. The master system 10 and the slave system 20 boot the CPUs 11 and 21, respectively in accordance with a boot program stored in the program ROM. Thus, the Related Art of FIG. 4 has a problem that the number of components is large because both of the master system 10 and the slave system 20 include the program ROM such as a mask ROM or FLASH. In particular, along with advancements in system configuration, recent multiprocessor systems often include two or more slave systems, so program ROMs as many as slave systems should be provided. The increase in the number of components becomes a serious problem.
Japanese Unexamined Patent Publication No. 2000-137671 discloses a technique regarding a control system using a multi-bus rack, and more particularly focuses on a technique of transferring a program from a ROM on a master substrate to a RAM on another substrate (slave substrate). Further, Japanese Unexamined Patent Publication No. 10-320366 discloses a technique of transferring a common boot program from a master CPU to a slave CPU to thereby boot the slave CPU. Japanese Unexamined Patent Publication No. 4-98448 discloses a technique of sharing a program ROM among plural CPUs in a multi-CPU memory system but gives no description of a multiprocessor system including a master system and a slave system. Further, Japanese Unexamined Patent Publication No. 2005-31796 discloses a technique of downloading a program to a communication device including plural CPUs from another communication device but gives no description of a multiprocessor system including a master system and a slave system.
The technique as disclosed in Japanese Unexamined Patent Publication No. 2000-137671 has a problem in that complicated hardware configuration is necessary for transferring the program because the program is transferred through a common memory bus from the master substrate to the slave substrate.
With regard to the technique as disclosed in Japanese Unexamined Patent Publication No. 10-320366, a common boot program from the master CPU is temporarily stored in a dual port RAM, and the slave CPU downloads the program and boots up. For such configuration, it is necessary to prepare an expensive dual port RAM and lay out memory bus lines on both sides of the RAM. This causes a problem in that the number of components and costs increase.